1. Field of the Invention
This invention relates to a video system and a scaler, more particularly to a video system and a scaler that perform frame synchronization.
2. Description of the Related Art
A video system comprises a decoder and a scaler. The decoder receives a video signal and decodes an image data component of the video signal to generate a decoded signal. The scaler receives the decoded signal, and modifies a frame size (resolution) associated with the decoded signal to generate a display signal output to a display panel.
Since a frequency of the video signal varies, the decoder must utilize a complex tracking mechanism and a complex circuit to track a clock control signal (such as a horizontal synchronization signal (HS), a vertical synchronization signal (VS), or a clock signal (CLOCK)) of the video signal. Similarly, the scaler needs to utilize a complex tracking mechanism (a closed-loop mechanism is conventionally utilized) to track a clock control signal output from the decoder for correctly displaying content of the video signal on the display panel.
FIG. 1(a) illustrates a conventional scaler. The scaler includes a scaling unit 91, an output unit 92, a tracking unit 93, and a clock generating unit 94. The tracking unit 93 receives a clock control signal that is output from the decoder, and generates a frequency control signal in accordance with the clock control signal and an output clock signal that is output from the clock generating unit 94. The clock generating unit 94 generates the output clock signal (including a horizontal synchronization signal (HS) and a clock signal (CLOCK)) in accordance with the frequency control signal. In other words, the output clock signal is fed back to the tracking unit 93 so that the tracking unit 93 and the clock generating unit 94 form a closed-loop circuit. Since the tracking unit 93 must refer to (that is, track) variations in the clock control signal and the output clock signal simultaneously for generating the frequency control signal, it can be inferred that an algorithm utilized by the tracking unit 93 is very complex.
FIG. 1(b) illustrates another conventional scaler. The scaler includes a scaling unit 91′, an output unit 92′, a tracking unit 93′, and a clock generating unit 94′. The tracking unit 93′ must track a clock control signal that is output from the decoder and an internal status (a data quantity) of a buffer (not shown) in the scaling unit 91′ simultaneously for generating a frequency control signal. The clock generating unit 94′ generates an output clock signal (including a horizontal synchronization signal (HS) and a clock signal (CLOCK)) in accordance with the frequency control signal. Since a frequency of the output clock signal directly affects the data quantity of the buffer, which is tracked by the tracking unit 93′, the tracking unit 93′ and the clock generating unit 94′ form a closed-loop circuit similar to that of the previously described conventional scaler of FIG. 1(a).
Although the conventional scalers utilizing a closed-loop mechanism for tracking are capable of displaying correctly the content of the video signal on the display panel, the closed-loop mechanism increases circuit complexity of the video system.